This application includes descriptions of algorithms that may be implemented by one or more computer programs. The owner of this application reserves the right to claim certain copyrights in said computer programs. The owner has no objection, however, to the reproduction by others of the descriptions herein of such algorithms if such reproduction is for the sole purpose of studying the disclosure to understand the invention or inventions described herein. The owner reserves all other copyrights in such computer programs, including the right to reproduce Such computer programs in machine-executable form.
1. Field of the Invention
The invention relates generally to memory systems that use inexpensive random access memory devices (e.g. DRAM devices). The invention relates more specifically to memory devices that may be programmably-calibrated while in-circuit.
2. Description of the Related Art
Dynamic memory or DRAM (dynamic random access memory) devices are well-known in the industry for providing inexpensive and relatively high-speed storage capabilities. The basic dynamic memory cell comprises a charge-storing capacitor and a gating element (e.g. a field effect transistor) for providing addressable access to the charge in the capacitor for sensing, refresh and overwriting.
Because of the simplicity of the basic dynamic memory cell, many such cells can be crammed economically into industry-standard sized integrated circuit (IC) dice. For example, present day home computers are typically provided with so-called SIMM""s (Single Inline Memory Modules) that have 8 or 9 IC packages mounted thereon with each such IC package providing 64 Mb (64 Mega-bits) of DRAM storage. Such SIMM""s may be used for providing the main system memory of the computers. Each IC device of the SIMM typically includes a monolithic silicon die or other semiconductor substrate with lithographically defined circuitry provided thereon or therein. The IC device further comprises a sealed package for protecting the substrate and its circuitry, and interconnect pins for providing signal coupling between the package-internal circuitry and external circuits. Multi-Chip Module (MCM) type packages may also be used.
There remains a long-felt desire in the industry to increase the storage density and speed of dynamic memory (e.g., DRAM) systems while simultaneously reducing costs. However, this is not a simple task. Part of the effort toward reduction of costs comes in the form of making ever-smaller dynamic memory cells. But that is not enough. Aside from a large number of dynamic memory cells, a dynamic memory device generally needs additional circuitry for organizing its dynamic memory cells into addressable words, refreshing data held in the memory cells, moving data along internal buses, and interfacing with external circuitry. All these additional circuits introduce varying delays to the data access times of the overall dynamic memory device.
Because of this, it has become difficult to mix and match different dynamic memory devices in a single system. For example, if a computer system requires so-called 70 nS (70 nanosecond) devices, it is not advisable to mix-in faster 60 nS devices while retaining the slower 70 ns devices. The differing response speeds of such mixed devices may create timing problems on the memory bus. Even if all the utilized devices are rated for a same 60 nS speed, sometimes timing problems may still arise if the mix of 60 nS devices is from different manufacturers. Tolerances may vary between manufacturers. Because of this each memory device may have slightly different parametric characteristics than that of its neighbors due to, for example, the use of different semiconductor technologies in their manufacture. This presents problems to users who have invested in a first set of memory chips from a first vendor and want to mix them in a same memory system with a second set of more modern memory chips obtained from a different vendor.
Despite such problems, the relatively low cost of dynamic memory (e.g., DRAM) devices has led to their incorporation into a wide variety of applications including serving as the main memory of both desktop and mobile computer systems, as well as providing image-storing services for real-time and high-resolution video systems. This broad range of applications imposes many demands on future generations of dynamic memory devices including desirabilities for: (a) providing yet-lower per bit cost and higher storage densities, (b) allowing for minimized power usage by each device, (c) providing for wide and sustainable read/write bandwidth capabilities, (d) reducing latency times between each access request and a corresponding read/write operation, (e) providing for easy scalability to deeper and/or wider data storage organizations, (f) permitting mixing and matching of memory devices in legacy systems that still use older technology devices, and (g) providing basic support for different kinds of hierarchical memory configurations.
In an attempt to meet a subset of these challenges, past generations of DRAM devices have evolved through a number of iterations over the years. Fast Page Mode (FPM) devices were early providers of higher speed access to previously opened pages of memory. Extended Data Out (EDO) devices provided for yet faster memory access by overlapping address decode and output operations. SDRAM (Synchronous DRAM) devices provided a higher speed interface by using synchronously-clocked data buses. DDR (Double Data Rate) devices began to take advantage of both edges on each clock pulse to increase throughput rate.
However, none of these evolutionary approaches (FPM, EDO, SDRAM, or DDR) are believed to be sufficient on their own for providing a general solution to the challenges that are expected to arrive in the coming years. Next-generation computer systems are expected to operate at ever-higher switching frequencies and use wider word sizes and deeper (larger) address spaces. Small amounts of skew between data and clock phases may become a problem. Small differences in the various delays that are imposed on parallel signals may become a problem. For example, delay differences may arise due to minor differences between parallel transmission lines that carry parallel clock and/or data signals (e.g., the delay differences may be due to slight mismatches of impedances on printed circuit board traces) and such differences may become a problem. As switching frequencies increase, problems with intersymbol interference, crosstalk, general noise, and so forth are expected to increase. A more comprehensive approach is needed for anticipating such problems and for providing flexible mechanisms to deal with such problems.
A Synchronous-Link Dynamic Random Access Memory (SLDRAM) System may be provided in accordance with the invention to include: (a) a command module for issuing command packets to uniquely addressable memory units and/or addressable collections of such units; (b) a high-speed command link for carrying the command packets; (c) one or more high-speed data links for carrying data corresponding to packet-commanded data-transfer actions; and (d) one or more, in-circuit programmably-calibratable SLDRAM modules each having one or more addressable memory units, where each SLDRAM module is capable of interfacing with the command link and at least one of the high-speed data links for appropriately responding to informational queries provided by command packets, for further appropriately responding to tuning (adjustment, or calibrating) commands provided by command packets, and for yet further appropriately responding to data addressing and other data-transfer-related commands provided by command packets.
A system initializing method in accordance with the invention comprises the steps of: (a) first initializing an SLDRAM system by broadcasting from a reference location (e.g., from pins of a memory controlling module) a predefined first synchronization sequence over command/address lines (e.g., CA(9:0)) and data lines (e.g., DQ(17:0)) of the system while simultaneously and synchronously outputting from the reference location a continuously-running clock train over one or more clock lines (e.g., CCLK, DCLK0, DCLK1) of the system for allowing one or more SLDRAM modules present in the system to each self-adjust local command-receiving and data-receiving circuits of the SLDRAM module to synchronously recognize the predefined first synchronization sequence at the locality of the self-adjusting SLDRAM module; (b) second initializing the SLDRAM system by sequentially assigning identification codes (ID""s and/or sub-ID""s) to individually-addressable, memory units within the in-system SLDRAM modules; (c) third initializing the SLDRAM system by sequentially commanding each in-circuit SLDRAM module to adjust output levels of the SLDRAM module""s data-clock driving and data-line driving circuits to levels acceptable to an in-circuit memory controller (command module); (d) fourth initializing the SLDRAM system by sequentially commanding each in-circuit SLDRAM module to respectively output a predefined second synchronization sequence (which can be the same as the first) over the data lines (e.g., DQ(17:0)) of the system while simultaneously and synchronously outputting from the commanded SLDRAM module, a continuously-running clock train over one or more data-clock lines (e.g., DCLK0, DCLK1) of the system, this for allowing the in-circuit memory controller to command adjustments (e.g., individual phase changes) to local data-outputting circuits and local data-clock outputting circuits of the sequence-outputting SLDRAM module so that the memory controller will be able to synchronously recognize the predefined second synchronization sequence at the locality of the memory controller; and (e) fifth initializing the SLDRAM system by sequentially determining data read and data write latency times of respective ones of the in-circuit, individually-addressable, memory units.
A system utilization method in accordance with the invention comprises the steps of: (a) synchronously issuing command packets from a reference location (e.g., from a memory controlling module) of an SLDRAM system using command/address lines (e.g., CA(9:0)) of the system and command-clock lines (e.g., CCLK/CCLK#) of the system for transmitting the command packets to one or more in-circuit-calibratable SLDRAM modules of the system, where first ones of the issued command packets individually or collectively address one or more individually-addressable, memory units within the SLDRAM modules and define a data-transfer operation to be carried out by the individually or collectively addressed memory units; and (b) causing the addressed memory units to responsively perform the defined data-transfer operation within a time slot that follows receipt by the memory unit of a respective command packet, where latency between the receipt of the respective command packet and the responsive performance the defined data-transfer operation is adjustable; and wherein second ones of the issued command packets individually address one or more of the individually-addressable, memory units and define one or more respective data-transfer latencies for the individually-addressed memory unit.
A pins and/or traces distribution. pattern in accordance with the invention, as seen across a plane that intersects the pins or the traces (which traces can be printed circuit board traces), is characterized by: one or plural linear series of pins/traces, with each series extending in a lateral first direction between outer extremes of a signal communicating path extending longitudinally in a second, generally orthogonal direction and wherein said pins/traces include: (a) a first pair of complementary command-clock pins/traces for respectively carrying complementary command-clock signals (CCLK, CCLK#), the first pair of command-clock pins/traces being disposed approximately midway between said outer extremes of said signal communicating path; (b) a set of command-packet carrying pins/traces for carrying command words (CA0:9) that are synchronized with the command-clock signals and define command-packets, the command-packet carrying pins/traces being disposed proximate to the first pair of command-clock pins/traces; (c) a packet-flagging pin/trace for carrying a FLAG signal that may be used to identify the beginning or ends of consecutive command-packets, the command-flagging pin/trace being disposed proximate to the command-carrying pins/traces; (d) second and third pairs of complementary data-clock pins/traces for respectively carrying complementary first data-clock signals (DCLK0, DCLK0#) and complementary second data-clock. signals (DCLK1, DCLK1#), the second and third complementary pairs of data-clock pins/traces being disposed proximate to the first pair of complementary command-clock pins/traces; (e) a set of data-word carrying pins/traces for carrying data-words (DQ0:17) that are synchronized with one or the other of the data-clocks (DCLK0, DCLK1), the set of data-carrying pins/traces being distributed symmetrically about the data-clock carrying pins/traces; and (f) data-output powering pins/traces for providing dedicated power rails (VDDQ, VssQ) for line-drivers that output signals onto the data-carrying pins/traces, the data-output powering pins/traces being distributed plurally and symmetrically adjacent to the data-word carrying pins/traces.
Other aspects of SLDRAM systems in accordance with the invention will become apparent from the below detailed description.